1. Field of the Invention
The present invention relates to a circuit device having a structure, in which a semiconductor chip and an interposer substrate are integrally coupled by a flip chip connection, and a fabrication process of the circuit device.
2. Description of the Related Art
Currently, circuit devices, such as IC (Integrated Circuit) and so forth, have been fabricated as independent chip parts, and are used in various electronic equipments. Such circuit device has a structure, in which a large number of lead terminals are arranged on a circumference of a semiconductor chip of a semiconductor circuit having large number of connection pads, the lead terminals are individually connected with the connection pads of the semiconductor chip by bonding wire, and inside portions of the semiconductor chip and the lead terminals are sealingly embedded in resin member.
In the circuit device of the construction set forth above, since a large number of lead terminals are projected outside of an outer periphery portion of the resin member, data communication can be established between the printed circuit on a printed circuit board (PCB) and a semiconductor circuit of the circuit device by mounting the circuit device on an upper surface of the PCB and connecting the lead terminals with the printed circuit.
However, in the recent years, downsizing and increasing of integration degree of the circuit device is in progress to cause increasing of number and density of the lead terminals. This causes difficulty in accurately connecting the lead terminals of the circuit device to the printed circuit on the PCB at user level. Furthermore, fine lead terminals lack strength to easily cause breakage of the lead terminals in handling at user level to spoil the circuit device.
In order to solve the foregoing problem, a semiconductor package as the circuit device of BGA (Ball Grid Array) structure has been developed. In the semiconductor package of the BGA structure, connection terminals are formed as spherical solder bump, which are, arranged entire area of a lower surface of the device as two-dimensional array. Therefore, arrangement density of the lead terminals can be lowered and breakage of the lead terminals is hardly caused.
One example of the conventional circuit device of BGA structure will be discussed hereinafter with reference to FIG. 15. It should be noted that FIG. 15 is a diagrammatically illustrated section showing an internal structure of the semiconductor package as the circuit device. On the other hand, for simplification of disclosure, up and down direction on the drawing is expressed as up and down direction of the device, simply.
As shown in FIG. 15, the semiconductor package 1 exemplifying the circuit device has a semiconductor chip 2 consisted of a semiconductor circuit integrated at high density. The semiconductor chip 2 is mounted on the upper surface of the interposer substrate 3. The semiconductor chip 2 is formed with a large number of connection pads (not shown) on the lower surface. On the other hand, the interposer substrate 3 is formed with a large number of connection pads (not shown) on both of the upper surface and the lower surface.
In greater detail, the interposer substrate 3 is formed with a large number of connection pads at the center portion of the upper surface at positions corresponding to the connection pads of the semiconductor chip 2 at high density, and large number of connection pads is formed over substantially entire area at low density. Then, the interposer substrate 3 is formed into a multi-layer structure and large number of printed circuits and through holes is formed in the upper surface, the lower surface and inside. A large number of connection pads on the upper surface and the lower surface are appropriately connected through the printed circuits and the through holes.
On each of these connection pads, a solder bump 4 is mounted. The connection pad on the lower surface of the semiconductor chip 2 and the connection pad on the upper surface of the interposer substrate 3 are mechanically connected by a solder bump 4 for electrical connection. It should be noted that within intervals between the solder bumps 4, an under-fill resin 5 of epoxy resin is filled. By the under-fill resin 5, mechanical connection between the lower surface of the semiconductor chip 2 and the upper surface of the interposer substrate 3 is reinforced.
Furthermore, in the semiconductor package 1 exemplified herein, sidewall form metallic stiffener 6 is engaged on the outer peripheral portion of the upper surface of the interposer substrate 3. On the upper surfaces of the stiffener 6 and the semiconductor chip 2, a top plate form metallic heat spreader 7 is bonded by a metal paste 8.
In the semiconductor package 1 of the construction set forth above, the semiconductor circuit is integrated on the semiconductor chip 2 at high density, and the connection pads are arranged on the semiconductor chip 2 at high density. On large number of connection pads on the upper surface of the interposer substrate 3 of the same arrangement, solder bumps 4 are connected individually. A large number of connection pads on the upper surface of the interposer substrate 3 are appropriately connected to a large number of connection pads arranged on the lower surface thereof at low density.
The conventional fabrication process of the semiconductor package 1 of the structure set forth above will be discussed briefly. At first, as various parts forming the semiconductor package 1, the semiconductor chip 2, the interposer 3, the stiffener 6, the heat spreader 7 and so forth are fabricated with respectively predetermined structures.
Next, the stiffener 6 is bonded on the outer periphery portion on the upper surface of the interposer substrate 3, and the semiconductor chip 2 is bonded on the center portion by the solder bump 4 by bonding connection. Then, the entire interposer substrate 2 with the stiffener 6 and the semiconductor chip 2 is washed by flux washing and dried. Then, O2 plasma process is performed. Within gaps between the interposer substrate 3 and the semiconductor chip 2, epoxy resin to be under-fill resin 5 is filled and cured to form the under-fill resin 5.
Then, the head spreader 7 is bonded on the upper surface of the semiconductor chip 2 by the metal paste 8 and also bonded on the stiffener 6 by an bonding agent 9, such as epoxy resin or the like. Finally, for each of large number of connection pads on the lower surface of the interposer substrate 3, the solder bumps 4 are loaded to complete the semiconductor package 1.
Upon fabrication of the semiconductor package 1 set forth above, the under-fill resin 5 is filled in order to improve mechanical connection strength of the semiconductor chip 2 and the interposer substrate 3. As a method of implantation of the under-fill resin 5, a liquid state resin is supplied from peripheral edge of the semiconductor chip by means of a dispensing nozzle mounting a syringes stocking the liquid state resin for making the high viscosity epoxy resin to penetrate into fine gaps between the semiconductor chip 2 and the interposer substrate by capillary phenomenon. However, long period is required for operation to make the liquid state resin to penetrate and a long required for curing the liquid state resin becomes longer than that of transfer molding using a tablet resin to degrade production efficiency. Furthermore, by penetration depending upon capillary phenomenon, internal void as a space not filled with the resin can be caused to make it difficult to enhance reliability of the package.
On the other hand, in the foregoing semiconductor package 1 is separately fabricated the interposer substrate 3 and the stiffener 6 and is then bonded. On the stiffener 6, the heat spreader 7 is bonded by epoxy resin. Therefore, number of process steps in fabrication and number of component parts are large to lower productivity. Also, since a plate form heat spreader 7 is bonded on the upper surface of the semiconductor chip 2 and the stiffener 6, it becomes necessary to adjust respect upper surfaces of the semiconductor chip 2 and the stiffener 6 in flush. This also servers for degrading productivity of the semiconductor package 1.
On the other hand, as a method for filling the under-fill resin, there has been disclosed in Japanese Unexamined Patent Publication No. Heisei 10-270477, a method, in which a through hole for filling resin is formed at a predetermined position of the circuit board and a resin is filled by applying a pressure on the resin with inserting the nozzle for supplying resin into the through hole. However, in order to bond the heat spreader on the upper surface of the semiconductor chip and the stiffener, large number of fabrication processes and component parts are required for lowering productivity.
Also, in Japanese Unexamined Patent Publication No. 2000-349203, there has been disclosed a fabrication process of a semiconductor device, in which the flip chip mounted semiconductor chip and the interposer are contacted with a cavity of a mold and a molten epoxy resin is filled from the side portion of the semiconductor chip under pressure. However, problems are encountered in that long period is required for filling the resin from the side portion of the semiconductor chip and in that sneaking of resin is caused since gap between the semiconductor chip and the interposer is narrow to cause internal void. Furthermore, due to breakage of the corner portion of the semiconductor chip by contact between the mold and the semiconductor chip or sneaking of resin to the back surface of the semiconductor chip by filling of the resin under pressure, degradation of external appearance can be caused.
The present invention has been worked out in view of the problems and drawbacks in the prior art as set forth above. Therefore, it is an object of the present invention to provide a resin sealing method and a resin sealing device of a semiconductor device which can perform resin sealing of an under-fill region and peripheral portion on the side of a semiconductor chip in the same process step, with shortening periods required for filling and curing the under-fill resin and avoiding formation of an internal void, and can simplify fabrication process and component parts.
In order to accomplish the above-mentioned object, according to the first aspect of the present invention, a semiconductor device, in which a semiconductor chip is connected to a wired substrate, comprises:
a through opening provided at a predetermined position of the wired substrate;
an under-fill region as a gap portion between the wired substrate and the semiconductor chip; and
a molded resin portion as peripheral portion along side edge of the semiconductor chip;
the molded resin portion and the through opening being sealed by resin;
a region where a distance between a connection surface with the semiconductor chip of the wired substrate and a resin surface of the molded resin portion is greater than a distance between the connection surface with the semiconductor chip of the wired electrode and a back surface of the semiconductor chip, being formed in the molded resin portion.
Since the surface of the semiconductor chip is formed at lower position than the resin surface of the molded resin, it can successfully present contact between the heat spreader and the semiconductor chip which otherwise damage the semiconductor chip in the subsequent process. Also, since it becomes unnecessary to form stiffener, fabrication process and component parts can be simplified as compared with the prior art to permit lowering of production cost.
Also, for achieving the above-mentioned object, according to the second embodiment of the present invention, a semiconductor device, in which a semiconductor chip is connected to a wired substrate, comprises:
a through opening provided at a predetermined position of the wired substrate;
an under-fill region as a gap portion between the wired substrate and the semiconductor chip; and
a molded resin portion as peripheral portion along side edge of the semiconductor chip;
the molded resin portion and the through opening being sealed by resin;
a stepped down portion as a recessed portion being formed surrounding the semiconductor chip in the molded resin portion as peripheral portion of the semiconductor chip.
By forming the stepped down portion in the molded resin portion, extra amount of metal paste and/or bonding agent to be used for securing the heat spreader on the semiconductor chip and/or the molded resin portion, can be captured to prevent occurrence of bonding failure.
In the preferred construction, the stepped down portion of the molded resin portion may have a tilted surface descending from an upper end surface of the semiconductor chip.
By providing the titled surface in the stepped down portion, it becomes possible to prevent penetration of the resin to the back surface of the semiconductor chip upon injection of the resin. Thus, failure by external appearance inspection can be reduced to improve yield of production.
Also, for achieving the foregoing object, it is preferred that the molded resin portion is formed with an over-hang portion overlapping with the upper end surface of the semiconductor device.
By forming the over-hang portion, the corner portions of the semiconductor chip can be protected by the resin to successfully prevent breakage of the semiconductor chip.
On the other hand, it is also possible for achieving the foregoing object that the molded resin portion is formed over substantially entire area of the wired substrate.
By forming the molded resin over substantially entire area, bowing of the semiconductor package in heat treatment in the subsequent process to improve reliability in mounting of the semiconductor package.
The resin may be injected through one or more through holes provided in the wired substrate for electrical connection under pressure for forming the under-fill region and the molded resin portion.
By using the through hole, it becomes unnecessary to form the through opening in the printed circuit board to contribute for down-sizing of the printed circuit board to contribute for reduction of weight and size of the semiconductor package.
For accomplishing the above-mentioned object, according to the third aspect of the present invention, a resin seal process of a semiconductor device for sealing an molding object, in which a semiconductor chip is connected with a wired substrate by a flip chip connection, by way of a transfer sealing method, comprises steps of:
setting the molding object within a mold;
clamping the mold;
injecting a resin into the resin flow passage provided in the mold for filling the resin through a through opening provided in the wired substrate from the resin flow passage for forming into a predetermined shape.
By making the resin flow passage provided in the mold corresponding to the semiconductor package, it becomes possible to fabricate variety of semiconductor packages with only exchanging the mold to simplify fabrication process. ON the other hand, in order to fill the resin from the through opening, it is possible to set the process for preferentially filling the resin of the under-fill region.
For accomplishing the above-mentioned object, it is preferred that filling of the resin is performed with varying injection amount of the resin per unit period according to elapsed time.
By varying the injection amount of the resin according to elapsed time, filing of the resin into particular portion of the semiconductor package can be assured. Resin sealing corresponding various kind of semiconductor packages can be performed.
For accomplishing the above-mentioned object, it is preferred that a plurality of the through openings and the resin flow passages are provided for performing filling of the resin at a plurality of portions.
By filing the resin from a plurality of positions, a period required for filing can be shortened by reducing production cost.
Preferably, filling of resin from the plurality of portions is performed with setting filling speed per route of the resin flow passages independently of each other.
By varying the filling speed per route of the resin flow passages, resin seal corresponding to the shape of the semiconductor package to be obtained can be performed to adapt for wide variety of products.
Preferably, filling of resin from a plurality of portions is performed with setting filling start timing per route of the resin flow passage independently of each other.
By varying filling start timing per route of the resin flow passages, resin seal corresponding to the shape of the semiconductor package to be obtained can be performed to adapt for wide variety of products.
For accomplishing the foregoing object, filling speed of resin into an under-fill region as a gap portion between the wired substrate and the semiconductor chip may be lower than a filling speed of the resin into a molded resin portion as peripheral portion of the semiconductor chip.
Since resin filling speed to the under-fill region can be higher than that of the mold resin portion, filing of the resin to the under-fill resin can be certainly performed to suppress formation of the internal void to improve reliability of the semiconductor package.
Preferably, filling timing of resin into an under-fill region as a gap portion between the wired substrate and the semiconductor chip may be earlier than a filing timing of the resin into a molded resin portion as peripheral portion of the semiconductor chip.
Filing of resin into the under-fill region can be done at early timing in comparison with filling in the mold resin portion for ensuring filing of the resin within the under-fill area to suppress formation of the internal void to improve reliability of the semiconductor package.
Preferably, filling of the resin is performed through one or more through holes provided in the wired substrate for electrical connection to make it equivalent to the through opening.
By utilizing the through hole, it becomes unnecessary to form the through opening in the wired substrate, downsizing of the wired substrate can be achieved to contribute for reduction of weight and size of the semiconductor package.
The resin seal process of a semiconductor device may further comprise step of setting a plurality of molding objects within the mold and clamping the mold for filing the resin for a plurality of semiconductor chips simultaneously.
Also, by filling the resin in a lump, number of semiconductor package to be fabricated within the unit period can be increased to contribute for lowering of production cost.
For accomplishing the above-mentioned object, according to the fourth aspect of the present invention, a resin sealing apparatus for resin sealing a molding object, in which a semiconductor chip is connected to the mold and a resin seal is formed in a shape of a cavity portion provided in the mold by a transfer seal method, comprises:
a resin flow passage formed as a space in the mold up to a position corresponding to a through opening provided in a wired substrate from a plunger introducing opening for performing injection of the resin into the mold.
In case of the mold exchangeable of the resin injection conduit and the runner, it is facilitated to exchange the resin flow passage to permit resin seal or encapsulation depending upon the shape of the semiconductor passage and thus to adapt for increased variety of the products.
Preferably, the resin flow passage is formed to a position corresponding to a through hole provided in the wired substrate for electrical connection.
By utilizing the through hole, it becomes unnecessary to form the through opening in the wired substrate to permit downsizing of the wired substrate to reduce weight and size of the semiconductor package.
The mold may be formed with a stepped down portion recessed with a tilted peripheral portion of the cavity portion in a region corresponding to the semiconductor chip.
By providing the stepped down portion, penetration of the resin to the back surface of the semiconductor chip can be prevented to contribute for improvement of yield in production.